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C++, Python, Verilog/VHDL

The systems emulated by the simulators implement concepts from computer networks, compiler theory, and embedded systems. This allowed me to determine the correctness and efficiency of a design without physically building the systems.

Some key projects include:

  • VHDL Synthesizer & Simulator

  • CSMA/CD Evaluator

  • Traffic Light Simulator (FPGA)

Simulators & Synthesizers: Projects


Holistic Learning


This VHDL 'compiler' produces circuit gate diagrams and simulations as outputs. Coded in Java, compiler concepts such as parsing, transformation, and optimization are implemented. Please note that this is only for combinational circuits (i.e, no for-loops, and if-else-while statements).


The CSMA/CD protocol will be simulated in two modes. In the persistent mode, all users listen to the line prior to transmitting. If traffic is sensed, they wait. When the line becomes free, packets are transmitted immediately. In the non-persistent mode, a user is ready to send data senses the line and commences transmission if free. If the line is busy, the user backs off for a random time before sensing resumes, and so on.


The goal of this project is to design a traffic light control system as a sequential circuit with a clock. The system controls two traffic lights on an intersection using a state machine. Sequential logic is implemented in this design (using flip-flops). The traffic light acts normally as a simple sequencer, to transit between green, amber, and red lights in real traffic light systems. As the board doesn't have yellow or orange LEDs, it is replaced with a flashing red light.

Simulators & Synthesizers: Files
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